A number of serial data bus driving circuits have been developed which eliminate high frequency noise components associated with the substantially instantaneous rise and fall times of the leading and trailing edges of the logic signals without distorting the data contained in the logic signals. One such wave shaping circuit is disclosed in U.S. Pat. No. 5,164,611 to Summe, which is assigned to the assignee of the present invention and is hereinafter incorporated by reference. The Summe patent discloses a wave shaping circuit that generates a relatively small amount of noise in the AM broadcasting band, is insensitive to ground offsets, and which operates with a minimal propagation delay between input logic signals and communication bus signals.
The Summe patent utilizes an exponential current source to provide a current to a regulator bus driver which charges and discharges a capacitor in response to the rising or falling edge of the data input signal. The exponential current source 26 is shown in FIG. 1 and includes a pair of NMOS transistors 22 and 24 which function as current sources. The NMOS transistor 12 is connected in series with and controls current source 22, which provides 95 microamps of current. Current source 24, which provides 5 microamps of current, is connected in parallel with the series connected transistor 12 and current source 22. PMOS transistor 44 is connected in series with the parallel combination of transistor 24 and series connected transistors 12 and 22, and forms a current mirror 40 with PMOS transistor 42. Current flowing through transistor 44 is thus mirrored to transistor 42 which provides this current through diode stack 30. Diode stack 30 includes diode connected NPN transistors 32-38 which are connected between the transistor 42 and ground. A two stage operational amplifier 46 comprises a first stage including differential input NPN transistors 48 and 50, PMOS load transistors 56 and 58, and current source 52. The second stage includes PMOS drive transistor 66 and current source 64. An integrating capacitor 60 and a zero cancelling resistor 62 are connected between the collector of transistor 50 and the base of transistor 48.
A linear to exponential converter 67 comprises a transistor 68 and a diode stack 70 which includes diode connected NPN transistors 72-76. The transistor 68 converts the linearly changing voltage designated VB, at its base, to an exponentially changing current at its collector according to the relationship EQU I=I.sub.s * exp(VB/4V.sub.t) (1)
where I is the current flow through the collector of transistor 68, I.sub.s is the saturation current of the transistor 68 which is constant for a given process, VB is voltage at node VB and V.sub.t is the thermal voltage which is a constant at a given temperature. A current mirror 78, comprising PMOS transistors 80 and 82, is connected with the collector of transistor 68 so that the transistor 68 collector current is reflected through PMOS transistor 84 to create a bias reference voltage EXPBIAS 86.
With reference to the waveforms 95 of FIG. 2, the exponential current source 26 operates in the following manner. A LOW logic input signal (signal 2A) at the gate of transistor 12 causes 5 microamps of current to flow through diode stack 30, thereby creating a reference voltage at node VA according to the relationship ##EQU1## where V.sub.t and I.sub.s are constants for a given process as previously discussed, and I.sub.m (signal 2B) is the current mirrored through the diode stack 30 from current mirror 40. In the steady state, the node voltage VA (signal 2C) is reflected to node VB (signal 2D), which is then converted back into a current by the linear to exponential converter 67.
When the logic input voltage at the gate of transistor 12 goes HIGH, the transistor 12 turns on and the current sourced from transistor 44 becomes the sum of the currents sunk by transistors 22 and 24, which totals 100 microamps. This current I.sub.m is mirrored through the diode stack 30 which causes an instantaneous increase in the node voltage VA. In accordance with equation (2), this increase is proportional to the logarithm of the current I.sub.m. Node VB attempts to follow node VA but is limited by the current through transistor 52, and by capacitor 60 according to the following relationship: ##EQU2## such that node VB rises at a fixed linear rate. Node voltage VB is impressed upon the base of transistor 68 which translates the linear voltage change to an exponential current through transistor 82 as previously discussed. With respect to equation (1) (signal 2E). This exponential current is then mirrored to transistor 80 to create the bias reference voltage EXPBIAS.
When the logic input voltage at the gate of transistor 12 goes LOW, the transistor 12 turns off and the current sourced from transistor 44 is again the current sunk only by transistor 24, which is 5 microamps. This current I.sub.m is then mirrored through the diode stack 30 which causes an immediate decrease in the node voltage VA in accordance with equation (2). Again, node VB tries to follow node VA but is limited by equation (3) above. Node voltage VB therefore decreases at a fixed linear rate which then results in an exponentially decreasing current through transistor 82 in accordance with equation (1). This current is then mirrored to transistor 80 to create the bias reference voltage EXPBIAS. In this manner, the exponential current source 26 provides an exponentially increasing output current in response to a HIGH logic level at the gate of transistor 12, and provides an exponentially decreasing output current in response to a LOW logic level at the gate of transistor 12.
The exponential current source 26 unfortunately includes some inherent disadvantages. First, due to the low impedance of the NPN diode string 30, the change in the node voltage VA is small when the current through current mirror 40 steps back and forth between 5 microamps and 100 microamps. This is evidenced by equation (2) which indicates that the node voltage increase and decreases only logarithmically with respect to the correspondingly increasing and decreasing current I.sub.m. Since node VB ultimately attempts to track node VA, equation (3) therefore requires capacitor 60 to have a relatively large value in order to obtain a desirable dt given a fixed current I.sub.52. Secondly, the diode stacks 30 and 70 require 8 NPN transistors. When fabricating exponential current source 26 on a monolithic integrated circuit, great area savings could be realized if capacitor 60 could be significantly reduced in size, and the diode stacks 30 and 70 could be replaced with more area efficient circuit components.